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Found 4 results

  1. I am trying to program the CPLD of a Xblast Lite that I built. Got the PCB from a friend. I flashed the tsop on the chip successfully. The cpld seems to be programming, but the xbox still frags when I try to boot with the chip. I am using the Flashcat USB programmer and software. The file I am flashing is XblastLiteV1.xsvf: https://github.com/Kekule-OXC/xblast_lite_cpld/tree/master/xilinx_ise I am not 100% sure that this is the right file, but flashcat seems to not work with jed files, so it is my only option at the moment. The output log of flashcat says that I flashed successfully, but first it says "SVF Player: Failed sending XSDRTDO command (line index: 20)" so I am wondering if that has anything to do with the fragging. Does anyone have experience with this? Here is the log from flashcat: Disconnected from FlashcatUSB Classic device Connected to FlashcatUSB Classic, firmware version: 4.56 BSDL database loaded: 26 total definitions JTAG TCK speed: 1 MHz JTAG chain detected: 1 devices JTAG TDI IR chain size: 8 bits Index 0: JEDEC ID 0x59604093 (Xilinx_XC9572XL_(VQ44)) JTAG engine setup successfully JTAG index 0 selected: Xilinx XC9572XL (IR length Checking for a device specific script to automatically load Button Hander::Calling Event: RunXSVF Running XSVF file in internal JTAG XSVF player SVF Player: Failed sending XSDRTDO command (line index: 20) SVF Player: TDO: 0x03FFFE SVF Player: Expected: 0x000001 SVF Player: Mask: 0x000003 XSVF file successfully played Button Hander::Calling Event: Done
  2. I’m in the process of building a few OpenXeniums myself and I haven’t quite hashed out a game plan for programming the CPLD. I don’t have a Xilink or JTAG programmer of any kind but I do have a raspberry pi. The most clear instruction I’ve found for using the pi is here. I like that using this method I can supposedly flash xeniumOS at the same time so I won’t have to hotswap. Has anyone else tried this or is able offer any guidance for using the pi?
  3. I put together a package with all the software needed. I also included the SVF file generated by ISE's impact. This is now the easiest method for programming OpenXenium's CPLD chip. After setup, it's just one click. Merry Christmas and enjoy! https://sites.google.com/view/xc9500xl-with-openocd-ft232r/home
  4. Hello World So I've finally found a Xblast Modchip but... broken one, before buying it, would be happy to hear any advices from the techy folks regarding this situation and what can be done. So seems like the guy who sells it, somehow succeded to crack that U4 chip, and cut a few legs on the Xilinx CPLD, which looks like - they can not be repopulated. The questions are: 1, What chip is U4? 2. Will the new replacement Xilinx XC9572XL CPLD need any firmware? (did not found anything on the xblast repository) 3. Will the SVF from Aladdin Xblast Mod work in this case? (as I know, to launch XBlast bios on Aladdin Modchip, the PLCC32 must have the bios itself, then CPLD also should be written with something) This is how the SVF for Aladdin CPLD LC4032V-XXT44 starts: ! Lattice Semiconductor Corp. ! Serial Vector Format (.SVF) File. ! User information: ! File name: C:\dev\perso\aladdin_xt_mods\1MB_LPCmod_banks\1mb_lpcmod_banks_epv.svf ! CREATED BY: Universal File Writer V2.48 ! CREATION DATE: Tue Dec 23 20:45:48 2014 ! Device: LC4032V(B) Erase,Program,Verify 1mb_lpcmod_banks.jed ! LATTICE_NOTE "Device" "LC4032V-XXT44" ! LATTICE_NOTE "Checksum/CRC" "B6F5" ! SVF Revision: D Format ! ABEL MACH432S30 ! NOTE ispLEVER Classic 1.7.00.05.28.13JEDEC Compatible Fuse File. ! NOTE Copyright (C), 1992-2014, Lattice Semiconductor Corporation. ! NOTE All Rights Reserved. : ! NOTE DESIGN NAME :1mb_lpcmod_banks ! NOTE DATE CREATED :Tue Dec 23 20:45:43 2014 ! NOTE DEVICE NAME :LC4032V-10T44I ! NOTE DEVICE TEMPLATE :M4S_32_30 ! NOTE PIN ASSIGNMENTS ! NOTE PINS portLCLK : 39 : in ! NOTE PINS portPWR : 26 : in ! NOTE PINS portHD : 9 : in ! NOTE PINS nportLRST : 2 : in ! NOTE PINS xportLAD_3_ : 21 : inout ! NOTE PINS fportLAD_3_ : 41 : inout ! NOTE PINS portLFRAME : 40 : out ! NOTE PINS portD0 : 31 : out ! NOTE PINS portX : 30 : out ! NOTE PINS portL1 : 29 : out ! NOTE PINS xportLAD_2_ : 22 : inout ! NOTE PINS xportLAD_1_ : 37 : inout ! NOTE PINS xportLAD_0_ : 38 : inout ! NOTE PINS fportLAD_2_ : 42 : inout ! NOTE PINS fportLAD_1_ : 43 : inout ! NOTE PINS fportLAD_0_ : 44 : inout ! NOTE NODES cnt1_0_ : A_M12 ! NOTE NODES cnt1_1_ : A_M14 ! NOTE NODES cnt1_2_ : A_M13 ! NOTE NODES inst_OSbnkctrl : B_M2 ! NOTE NODES OSbnkSW_1_ : B_M12 ! NOTE NODES inst_OSKill : B_M7 ! NOTE NODES inst_init : B_M13 ! NOTE NODES inst_direction : A_M5 ! NOTE NODES inst_OSdisable : B_M14 ! NOTE NODES inst_IOcyc : A_M6 ! NOTE NODES iportMCUreg_0_ : A_M8 ! NOTE NODES iportMCUreg_1_ : B_M11 ! NOTE NODES iportMCUreg_2_ : A_M9 ! NOTE NODES iportMCUreg_3_ : A_M15 ! NOTE NODES OSbnkSW_0_ : B_M15 ! NOTE NODES signaltypeLpc_0_ : A_M10 ! NOTE NODES signaltypeLpc_1_ : A_M7 ! NOTE NODES N_81_i : B_M5 ! NOTE NODES N_24_i : B_M6 ! NOTE NODES portL1_0 : A_M11

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Board startup date: April 23, 2017 12:45:48
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